Giacomo has more than 18 years of proven experience in analog mixed signal design with a focus on high speed links. Before joining Chronos Tech, Giacomo was a project lead and architect at Intel Custom Foundry working on the latest ultra-high speed multi-standard Serdes in FinFET technology. Giacomo’s breadth of expertise ranges from architectural definition to high volume manufacturing. He has been involved in all aspects of the product life cycle of a chip, having successfully taped out multiple products in BiCMOS, planar and FinFET CMOS technology. Giacomo has a Laurea Doctorate degree in Electrical Engineering and an MBA. He is also the inventor of various US Patents in the electrical field.
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VP of Engineering
Stefano is a veteran in complex mixed-signal chip design. Prior to founding Chronos Tech, Stefano covered several technical leadership positions in the industry both as Director of Engineering as well as Lead Architect. Stefano brings expertise in the area of high-speed design, advanced SerDes, low-power techniques, DSP and adaptation algorithms, FinFET technology, top down methodology; with depth ranging from architectural investigation to final product and IP tuning and optimization. Stefano has a Laurea Doctorate degree in Electronics Engineering, and a Master in Business Administration. He holds many US patents in the field of high speed design and computer architectures.
Sr. Technical Director
Matthew has 18 years of SoC integration experience across technologies and markets. Before joining Chronos Tech, he was Senior Principal Design Engineer at Broadcom, leading implementation activities for wireless communication chips. Matthew has brought many new product lines to first silicon with expertise in physical design, IP integration, timing closure, power analysis, and manufacturing processes. Matthew has a B.S. in Electrical Engineering from California Polytechnic State University, San Luis Obispo.
Founded in 2015 by semiconductor industry veterans, Chronos Tech was established with the goal to overcome the hurdles of modern SoC design. The design community needed innovation to help conquer the growing problems in timing closure, routing congestion, poor yield, and schedule delays.
Through a deep evaluation of existing technologies, as well as creative design and combination of new ones, we found the solutions. Today as we continue our search for the next technological breakthroughs in IP and SoC design, we are glad to offer our patented solutions for customer evaluation and deployment.
9444 Waples St. #165, San Diego, CA 92121