Two different examples of routing reduction by applying Chronos technology are shown above.  The first one (SoC1) represents a high frequency dominant SoC such as a mobile phone or networking chip, where busses can reach very high frequencies.  In this example the original 50,000 routes at top level are reduced to 17,513 routes, bringing around 65% reduction in congestion.  Compression can be pushed even further when the SoC is Low Frequency dominant (second example SoC2) such as in IoT or microcontroller application.  In this case the overall routing congestion is reduced by over 80%.

​​Chronos clockless temporal compression mitigates the routing and area overhead previously discussed, and actually, moves the needle in the opposite direction.  It enables the serialization of the data at higher speeds according to a specific compression ratio while minimizing clock distribution.  This ratio can be adjusted at the time of synthesis thereby allowing the architect to trade routability vs link speed.  ​​​Compression ratio and library type can be tuned on a channel by channel basis.  The maximum compression ratio per channel is limited by the Maximum Equivalent Speed (MSPD) of the signaling traveling within a Chronos channel.  MSPD is a parameter dependent on the process technology in which the SoC is implemented.  

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Accugauge technology allows the recovery of most timing margins by enabling a real-time measurement of link performance.

AccuGauge allows true silicon performance evaluation  on a specific PVT condition, enabling accurate trade-off in terms of power, speed and reliability. These features facilitate testing and margining for each individual channel, simplifying EV, qualification, and DPM analysis. 

This unique in-circuit probing capability can also be used to throttle on-the-fly voltage and speed, while still guaranteeing functionality and performance per individual link.   

​​Latency reduction is another added benefit of Chronos Link.  Latency is one of the most important parameter in system performance.  The following diagram shows a direct comparison between a traditional pipelined link vs the equivalent  Chronos Link.  As shown below, the Chronos Link  is able to outperform the traditional pipelined link even at significant compression ratios.  

*Assuming MSPD = 3GHz

​​One of the most well-known and effective side-channel attacks today leverages the information leaked through the power consumption of the chip. Differential Power Analysis (DPA), for example, makes use of effective statistical algorithm to retrieve internal information to be used to break the security of the system.

Chronos technology is very effective in mitigating DPA attacks due to its unique power consumption profile.  The right-hand picture above shows the difference between the power profile of a standard digital channel vs the power profile of the same channel implemented with Chronos Link.  The current profile of the standard channel has very high peaks, which are correlated to the data pattern of the data being transmitted.  Instead, with the Chronos Link, the current profile shows a very even behavior during the transaction, and there is no direct correlation between the power utilized and the data being transmitted.  Another measurable effect of the change in power profile is the significant reduction in Electromagnetic Interference (EMI), the electromagnetic emission of a Chronos channel has much lower power peaks with energy more evenly spread out through the frequency spectrum.  The result of adding Chronos Technology to a communication channel is a significant increase in security.

Chronos Link

​​The benefits of a compressed DI channel would be greatly overshadowed if the technology was not able to interface seamlessly with standard SoC protocols commonly used in modern designs.  Chronos integrates directly with the most common modern interfaces (i.e. AMBA AXI, ACE, OCP, etc.) as well as with any custom protocol used within dedicated IP and/or NoC with flow control.  Chronos is also able to replace non-timing critical interfaces such as control registers, fuses, Interrupts, etc., thereby drastically reducing routing congestion at top level.

​On the right hand side is shown an example of SoC  design based on the award winning RISC-V architecture in FinFET technology, where Chronos seamlessly replaces all of the top level fabric  and auxiliary interfaces.  The end result shows reduction in routing, area and power as well as a boost in performance due to a decrease in total data-path latency. 

Traditional digital interconnect performance is limited by margins added to overcome clock jitter, PVT and on chip variation, as well as general timing margins and aging. 

Chronos Link is specifically designed with the goal of enabling the next generation of complex SoCs in the latest FinFET nodes.  It aims at enabling robust and secure on-chip and off-chip communication, while drastically reducing interconnect overheads.  Such unique characteristics result in substantial area reduction, effortless integration of IPs, resilience to delay variation and enhanced security; thereby addressing the key challenges in current SoC design.  

Chronos Tech patented technology is founded on the synergy of four main elements:

  • Delay-Insensitive channels
  • Clockless temporal compression
  • Compatibility with industry standard SoC protocols
  • AccuGauge embedded performance measurement technology

​Delay-Insensitive (DI) channels move the validity of the data from the clock edge to the data itself using a choice of data encoding and “handshake” protocol.  To practically leverage the benefits of DI channels in silicon we rely on the usage of Quasi-Delay-Insensitive (QDI) circuits.  In a QDI circuit, there is no need to provide a clock signal to determine a starting time for a computation.  Instead, the arrival of data to the input of a sub-circuit triggers the computation to start.  Consequently, the next computation can be initiated immediately when the result of the first computation is completed. 

The benefits of delay insensitivity have been long known to include resilience to PVT, and with that we leveraged simplification of timing closure as well as significant reduction in TTM.  In the past, this advantage was usually offset by the significant increase in routing requirements and area.  Additionally, the use of non-standard design methodology and tools caused industry resistance and decreased  the engineering confidence level on a successful tape-out.  Chronos Technology brings a solution to all the above concerns, mitigating the risk factors while exploiting the benefits.  ​​​

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